DBSWP=0, DBGEN=0, EN1588=0, SLEEP=0, MAGICEN=0, ETHEREN=0
Ethernet Control Register
RESET | Ethernet MAC Reset |
ETHEREN | Ethernet Enable 0 (0): Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 1 (1): MAC is enabled, and reception and transmission are possible. |
MAGICEN | Magic Packet Detection Enable 0 (0): Magic detection logic disabled. 1 (1): The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. |
SLEEP | Sleep Mode Enable 0 (0): Normal operating mode. 1 (1): Sleep mode. |
EN1588 | EN1588 Enable 0 (0): Legacy FEC buffer descriptors and functions enabled. 1 (1): Enhanced frame time-stamping functions enabled. |
DBGEN | Debug Enable 0 (0): MAC continues operation in debug mode. 1 (1): MAC enters hardware freeze mode when the processor is in debug mode. |
STOPEN | STOPEN Signal Control |
DBSWP | Descriptor Byte Swapping Enable 0 (0): The buffer descriptor bytes are not swapped to support big-endian devices 1 (1): The buffer descriptor bytes are swapped to support little-endian devices |